The "pinned" photodiode incorporates a p+ implant above the light sensitive structure within each pixel. It permits the total transfer of charge onto the measurement node under the control of the transfer gate T1.

 

Since the capacitance of the measurement node (the n+ implant shown in the diagram) is very much lower than the capacitance of the photodiode, the voltage change sensed by transistor T4 is much higher resulting in a lower input-referenced read noise.

 

A further advantage of this pixel topology is that low-frequency noise in the output amplifier can be greatly suppressed. This is explained further in the Reset Noise section.

 

E. Fossum.  A Review of the Pinned Photodiode for CCD and CMOS Image Sensors.

 

N.Teranishi. No image lag photodiode structure in the interline CCD image sensor.